The data path contain Arithmetic Logic Unit ( ALU), data registers, flag register and work register; 数据通道由ALU、数据寄存器、标志寄存器、工作寄存器组成;
Then, the thesis, based on March C-algorithm, shadow read and shadow write technologies, put forwards BIST arithmetic for the 20-port register file. 之后本文在MarchC-算法的基础上,结合shadowread和shadowwrite技术,首次提出了针对20端口寄存器文件的BIST算法。
The digit signal processor embodies the center arithmetic logic unit, Multiplier unit, Shifter unit, Sequencing unit, Auxiliary register unit, interception unit. 数字信号处理器包含了中央算术逻辑单元、乘法器单元、移位器单元、排序器单元、辅助寄存器单元、中断单元的设计。
In FPGA, CPU IP Core have necessary arithmetic logic unit ( ALU), register stack, instruction buffer, Jump-counter, instruction-set, and optimize the performance of CPU based on the architecture of FPGA. 在FPGA内部不仅实现了CPU必需的算术逻辑器、寄存器堆、指令缓冲、跳转计数、指令集,而且针对FPGA内部的结构特点对设计进行了地址和数据的优化。